The invention relates to an integrated circuit (IC) with clock distribution means for supplying clock signals
A prior art IC includes a plurality of input terminals, input flip-flops (FFs) connected to the input terminals, a plurality of output terminals, output FFs connected to the output terminals, a logic circuit network provided between the input and output FFs and made up of a combinational logic circuit and a plurality of FFs, and a clock distribution circuit for distributing to all the FFs clock signals which are identical in clock period and phase with each other. Such prior art ICs are mounted on a substrate and electrically interconnected by signal lines provided in the substrate, as disclosed in U.S. Pat. No. 4,398,208. Since clock signals of the same phase are applied to the output FFs of one IC and the input FFs of the other IC, the maximum-allowable-signal-propagation delay time of signal lines which interconnect those ICs has to be less than the clock period T of the clock signals. This gives rise to a disadvantage when the clock period is reduced with the intention of increasing the operation rate of the ICs. Specifically, although a decrease in the clock period is not critical within the individual ICs because the signal lines formed therein are extremely short, it prevents output signals of the output FFs of one IC from being correctly taken in by the input FFs of the other IC because the clock period becomes less than the maximum allowable signal propagation delay time.